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Sheet目录3753

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PIC16F946

DS41265A-page 186

Preliminary

2005 Microchip Technology Inc.

15.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value.

When

match

occurs,

the

RC5/T1CKI/CCP1/SEG10 pin is:

Driven high

Driven low

Remains unchanged

The action on the pin is based on the value of control

bits CCP1M<3:0> (CCP1CON<3:0>). At the same

time, interrupt flag bit CCP1IF is set.

FIGURE 15-4:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

15.2.1

CCP PIN CONFIGURATION

The user must configure the RC5/T1CKI/CCP1/SEG10

pin as an output by clearing the TRISC<5> bit.

15.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode, or Synchro-

nized Counter mode, if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

15.2.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen, the

RC5/T1CKI/CCP1/SEG10 pin is not affected. The

CCPIF bit is set, causing a CCP interrupt (if enabled).

15.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special event trigger output of CCP2 resets the

TMR1 register pair and starts an A/D conversion (if the

A/D module is enabled).

15.3

PWM Mode (PWM)

In Pulse-Width Modulation mode, the CCPx pin pro-

duces up to a 10-bit resolution PWM output. Since the

RC5/T1CKI/CCP1/SEG10 pin is multiplexed with the

PORTC data latch, the TRISC<5> bit must be cleared

to make the RC5/T1CKI/CCP1/SEG10 pin an output.

Figure 15-5 shows a simplified block diagram of the

CCP module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 15.3.3

“Setup for PWM Operation”.

Note:

Clearing the CCP1CON register will force

the RC5/T1CKI/CCP1/SEG10 compare

output latch to the default low level. This is

not the PORTC I/O data latch.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

Match

RC5/T1CKI/

TRISC<5>

CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

CCP1/SEG10

Note:

The

special

event

trigger

from

the

CCP1and CCP2 modules will not set inter-

rupt flag bit TMR1IF (PIR1<0>).

Note:

Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

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